The invention relates to a sigma-delta A/D converter with minimal current load of the reference voltage sources.
FIG. 1 shows a block circuit diagram of a sigma-delta A/D converter according to the prior art. The sigma-delta A/D converter receives an analog input signal at the input E, which is fed to a subtraction element S. In the subtraction element S the output signal of a multi-bit D/A converter is subtracted from the analog input signal and is fed to an integrator. The integrator integrates the input signal and outputs the integrated signal to a quantizer. The quantizer is an analog-to-digital converter with a low resolution which outputs the digitized output signal to an output A of the sigma-delta A/D converter. The digitized output signal is connected via a feedback line to the input of the multi-bit D/A converter. The digitized output signal of the quantizer is converted by the multi-bit D/A converter into an analog signal and is subtracted in the subtraction element S from the input signal at the input E.
FIG. 2 shows an embodiment of a sigma-delta A/D converter employing SC circuitry (SC switched capacities: switchable capacitors). The prior art sigma-delta A/D converter shown in FIG. 2 is a fully differential sigma-delta A/D converter having two signal inputs VINA and VINB. Also provided are reference voltage sources VREFP and VREFN which can be connected by controllable switching devices to capacitors C1A, C2A, . . . CLA as well as capacitors C1B, C2B, . . . CLB. The capacitors may furthermore be connected by switching devices to the analog signal inputs VINA, VINB.
On the output side, the capacitors C1A, C2A, . . . CLA as well as C1B, C2B, . . . CLB can be connected by switching devices n and a common ground line to ground VGND or to an integrator.
In the sigma-delta A/D converter shown in FIG. 2, the integrator contains an operational amplifier with one inverting and one non-inverting input as well as two output lines, with integration capacitors CINT being connected between the signal inputs and signal outputs of the operational amplifier in each case. Connected downstream of the integrator is a quantizer for analog-to-digital conversion of the voltage between the two output lines of the operational amplifier. The digitized signal present at the output of the quantizer is fed via a feedback line to a control logic element which supplies control signals for controlling the switching devices.
During a sampling phase PHl1, the capacitors C1A, C2A, CLA are connected by switches on the one hand to the first analog input line VINA and on the other hand to ground VGND. During the sampling phase PHL1, the capacitors C1B, C2B, . . . CLB are connected by switching devices on the one hand to the second analog input signal VINB and on the other hand to ground VGND. During the sampling phase, all switches indicated by xe2x80x9cPHL1xe2x80x9d in FIG. 2 are closed.
Upon completion of the sampling phase PHL1, the switches indicated by PHl1 in FIG. 2 are opened and the capacitors C1A, C2A, . . . CLA are connected by the switches indicated by PHL2 to the non-inverting input (+) of the operational amplifier and to the first integration capacitor CintA for charge transfer. At the same time, the capacitors C1B, C2B, . . . CLB are switched by the switches indicated by PHL2 to the inverting input (xe2x88x92) of the operational amplifier and to the second integration capacitor CintB for charge transfer. At the same time, in each case the left capacitor plates of the capacitors C1A, C2A, . . . CLA and C1B, C2B, . . . CLB are connected to the reference voltage source VREFP or to the reference voltage source VREFN respectively in accordance with the control instructions generated by the control logic element.
Upon completion of the integration phase PHL2, an output voltage VOUTP(i) is present at the output of the integrator, i.e. between the two output lines of the operational amplifier, which output voltage depends on the preceding value VOUTP(ixe2x88x921), the analog input voltage VINA (ixe2x88x92xc2xd), the number of capacitors CjA whose left capacitor plate is connected to the positive reference voltage source VREFP during the integration phase, and the number n (i) of capacitors CjA whose left capacitor plate is connected to the negative reference voltage source VREFN during the integration phase.
The output voltage VOUTP(i) is obtained here using the following equation:                                                         V              OUTP                        ⁡                          (              i              )                                =                                                                                          V                    OUTP                                    ⁡                                      (                                          i                      -                      1                                        )                                                  +                                                                            V                      INA                                        ⁡                                          (                                              i                        -                                                  1                          /                          2                                                                    )                                                        ·                                                            L                      ·                                              C                        jA                                                                                    C                      int                                                                      -                                                      p                    ⁡                                          (                      i                      )                                                        ·                                      "LeftBracketingBar"                                          V                      REFP                                        "RightBracketingBar"                                    ·                                                            C                      jA                                                              C                      int                                                                      +                                                      n                    ⁡                                          (                      i                      )                                                        ·                                      "LeftBracketingBar"                                          V                      REFN                                        "RightBracketingBar"                                    ·                                                            C                      jA                                                              C                      int                                                                                  ⩵                        =                                                                                V                    OUTP                                    ⁡                                      (                                          i                      -                      1                                        )                                                  +                                                                            V                      INA                                        ⁡                                          (                                              i                        -                                                  1                          /                          2                                                                    )                                                        ·                                                            L                      ·                                              C                        jA                                                                                    C                      int                                                                      -                                                                            (                                                                        p                          ⁡                                                      (                            i                            )                                                                          -                                                  n                          ⁡                                                      (                            i                            )                                                                                              )                                        ·                                          V                      REF                                        ·                                                                  C                        jA                                                                    C                        int                                                                              ⁢                                      xe2x80x83                                    ⁢                  with                  ⁢                                      xe2x80x83                                    ⁢                                      V                    REF                                                              =                                                "LeftBracketingBar"                                      V                    REFP                                    "RightBracketingBar"                                =                                  "LeftBracketingBar"                                      V                    REFN                                    "RightBracketingBar"                                                                    ;                            (        1        )            
The number of capacitors CjA whose left capacitor plate is connected to the positive reference voltage source VREFP during the integration phase is obtained here using the following equation:                                           p            ⁢                          xe2x80x83                        ⁢                          (              i              )                                =                                    round              ⁡                              [                                                      L                    /                    2                                    ·                                      (                                          1                      +                                                                                                    V                            DIG                                                    ⁡                                                      (                            i                            )                                                                                                    V                          REF                                                                                      )                                                  ]                                       less than =                          L              ⁢                              xe2x80x83                            ⁢              for              ⁢                              xe2x80x83                            ⁢                                                V                  DIG                                ⁡                                  (                  i                  )                                                       greater than =            0                          ;                            (        2        )            
where VDIG is the output signal of the quantizer.
The number of capacitances CjA whose capacitor plate is connected to the negative reference voltage source VREFN during the integration phase is obtained using the following equation:                                           n            ⁡                          (              i              )                                =                                    round              ⁡                              [                                                      L                    /                    2                                    ·                                      (                                          1                      -                                                                                                    V                            DIG                                                    ⁡                                                      (                            i                            )                                                                                                    V                          REF                                                                                      )                                                  ]                                       less than =                          L              ⁢                              xe2x80x83                            ⁢              for              ⁢                              xe2x80x83                            ⁢                                                V                  DIG                                ⁡                                  (                  i                  )                                                       less than =            0                          ;                            (        3        )            
where VDIG is the output signal of the quantizer. The total number of capacitances whose left capacitor plate in each case is connected to the positive reference voltage source during the integration phase and of capacitances whose left capacitor plate is connected to the negative reference voltage source VREFN during the integration phase is constant here.
p(i)+n(i)=L=const.,xe2x80x83xe2x80x83(4)
where L is the total number of capacitors.
So that the total charge is fully integrated, all capacitors are connected to the input of the operational amplifier during the integration phase.
The load of the reference voltage sources VREFP, VREFN with the prior art sigma-delta A/D converter shown in FIG. 2 is greatly signal-dependent.
For VDIG(i)xcx9cVINA(i) and VINA(i) greater than 0, the charge transfer at the positive reference voltage source caused by the analog input signal VINA(i) is calculated using the following equation:                     "AutoLeftMatch"                                            "LeftBracketingBar"                                                dq_V                  REFP                                ⁢                                  (                  i                  )                                            "RightBracketingBar"                        =                                                            p                  ⁡                                      (                    i                    )                                                  ·                                  (                                                            V                      REFP                                        -                                                                  V                        INA                                            ⁡                                              (                        i                        )                                                                              )                                ·                                  C                  jA                                            =                                                round                  [                                                            L                      /                      2                                        +                                                                  L                        /                        2                                            ·                                                                                                    V                            DIG                                                    ⁡                                                      (                            i                            )                                                                                                    V                          REF                                                                                                      ]                                ·                                  (                                                            V                      REFP                                        -                                                                  V                        INA                                            ⁡                                              (                        i                        )                                                                              )                                ·                                                      C                    jA                                    ~                                      (                                                                                            L                          /                          2                                                ·                                                  V                          REF                                                                    -                                                                        L                          /                          2                                                ·                                                                              V                            INA                                                    ⁡                                                      (                            i                            )                                                                                              +                                                                        L                          /                          2                                                ·                                                                              V                            DIG                                                    ⁡                                                      (                            i                            )                                                                                              -                                                                        L                          /                          2                                                ·                                                                                                                                            V                                INA                                                            ⁡                                                              (                                i                                )                                                                                      ·                                                                                          V                                DIG                                                            ⁡                                                              (                                i                                )                                                                                                                                          V                            REF                                                                                                                )                                                  ·                                                                            C                      jA                                        ~                    L                                    /                  2                                ·                                  C                  jA                                ·                                  V                  REF                                ·                                  (                                      1                    -                                                                                                                        V                            INA                                                    ⁡                                                      (                            i                            )                                                                          2                                                                    V                        REF                                                                              )                                                              ;                                    (        5        )            
The charge transfer at the negative reference voltage source is obtained using the following equation:                     "AutoLeftMatch"                              "LeftBracketingBar"                                          dq_V                REFN                            ⁢                              (                i                )                                      "RightBracketingBar"                    =                                                    n                ⁡                                  (                  i                  )                                            ·                              (                                                      "LeftBracketingBar"                                          V                      REFP                                        "RightBracketingBar"                                    +                                                            V                      INA                                        ⁡                                          (                      i                      )                                                                      )                            ·                              C                jA                                      =                                          (                                  L                  -                                      round                    [                                                                  L                        /                        2                                            +                                                                        L                          /                          2                                                ·                                                                                                            V                              DIG                                                        ⁡                                                          (                              i                              )                                                                                                            V                            REF                                                                                                                ]                                                  )                            ·                              (                                                      "LeftBracketingBar"                                          V                      REFN                                        "RightBracketingBar"                                    +                                                            V                      INA                                        ⁡                                          (                      i                      )                                                                      )                            ·                              (                                                                            ~                                              (                                                                                                            L                              /                              2                                                        ·                                                          V                              REF                                                                                +                                                                                    L                              /                              2                                                        ·                                                                                          V                                INA                                                            ⁡                                                              (                                i                                )                                                                                                              -                                                                                    L                              /                              2                                                        ·                                                                                                                                                                V                                    DIG                                                                    ⁡                                                                      (                                    i                                    )                                                                                                  ~                                L                                                            /                              2                                                        ·                                                                                                                                                                V                                    INA                                                                    ⁡                                                                      (                                    i                                    )                                                                                                  ·                                                                                                      V                                    DIG                                                                    ⁡                                                                      (                                    i                                    )                                                                                                                                                              V                                REF                                                                                                                                    )                                                              ·                                                                                            C                          j                                                ~                        L                                            /                      2                                        ·                                          C                      jA                                        ·                                          V                      REF                                        ·                                          (                                              1                        -                                                                                                                                            V                                INA                                                            ⁡                                                              (                                i                                )                                                                                      2                                                                                V                            REF                            1                                                                                              )                                                        ;                                                                                        (        6        )            
If both analog signal inputs VINA(i) and VINB(i) are included, the value and the effective current load of the reference voltage sources are doubled.
The effective current load of the reference voltage sources for the prior art sigma-delta A/D converter, as illustrated in FIG. 2, is then as follows:                                                         Ceff              VREF                        ⁡                          (              i              )                                =                      L            ·                          C              j                        ·                          (                              1                -                                                                            (                                                                        V                          INA                                                ⁢                                                  (                          i                          )                                                                    )                                        2                                                        V                    REF                    2                                                              )                                      ;                            (        7        )            
The maximum effective load of the reference voltage sources is obtained with VINA(i) xcx9c0 and is:
Ceff_maxxe2x80x94VREF=Lxc2x7Cj;xe2x80x83xe2x80x83(8)
The minimum value of the effective load of the reference voltage sources is obtained for the value VINA(i)xcx9cVREF:
Ceff_minxe2x80x94VREF=0.xe2x80x83xe2x80x83(9)
As can be seen from the above equations, the current load of the reference voltage sources in the prior art sigma-delta A/D converter, as illustrated in FIG. 2, depends on the analog input signal. The signal-dependent load of the reference voltage sources leads to non-linear distortions and limits the resolution of the prior art sigma-delta A/D converter.
It is therefore the object of the present invention to create a sigma-delta A/D converter in which the current load of the reference voltage sources is minimal.
According to the invention, this object is achieved by a sigma-delta A/D converter having the features specified in Claim 1.
Further advantageous refinements of the sigma-delta A/D converter according to the invention emerge from the subclaims.
The invention creates a sigma-delta A/D converter having at least one analog signal input for applying an analog input signal, a subtraction element having a plurality of capacitors for sampling the input signal during a sampling phase, it being possible during an integration phase to switch the capacitors to reference voltage sources depending on control signals, an integrator for integrating the output signal of the subtraction element during the integration phase, a quantizer for analog-to-digital conversion of the output signal of the integrator for outputting a digitized output signal to a digital signal output, and having a control logic element for generating the control signals in such a way that the current load of the reference voltage sources is minimized during the integration phase.
In an advantageous refinement of the sigma-delta A/D converter according to the invention, first switching devices are switched by control signals of the control logic element to connect the reference voltage sources to the capacitors during the integration phase.
In a further advantageous refinement of the sigma-delta A/D converter according to the invention, second switching devices are switched by control signals of the control logic element to connect the capacitors to the analog signal input during a sampling phase.
In a further advantageous refinement of the sigma-delta A/D converter according to the invention, third switching devices are switched by control signals of the control logic element to connect the capacitors to the integrator during the integration phase.
The control signals are preferably generated depending on the digitized output signal of the quantizer, the potential difference between the reference voltage sources and the number of capacitors.
In a preferred embodiment of the sigma-delta A/D converter according to the invention, the capacitors have the same capacitance.
Three reference voltage sources are preferably provided.
In a preferred embodiment of the sigma-delta A/D converter according to the invention, a first reference voltage source having a reference potential, a second reference voltage source having a positive potential and a third reference voltage source having a negative potential are provided.
The negative potential of the third reference voltage source and the positive potential of the second reference voltage source are preferably symmetrical to the reference potential of the first reference voltage source.
The sigma-delta A/D converter according to the invention is preferably of a differential design with two analog signal inputs.
A low-pass filter is preferably connected downstream of the digital signal output.
In a preferred embodiment of the sigma-delta A/D converter according to the invention, the integrator has an operational amplifier and at least one integration capacitor.
The quantizer preferably has a relatively low signal resolution in comparison with the signal resolution of the sigma-delta A/D converter according to the invention.
The operational amplifier within the integrator preferably has a very high-resistance signal input.